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LCMXO3L-4300E-5UWG81CTR FPGA
: 92 kbit
: 34 kbit
: 900 Mb/s
: 1.2 V
: 0 C
: + 85 C
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产品信息
LCMXO3L-4300E-5UWG81CTR
FPGA - 现场可编程门阵列 MachXO3, 4320 LUTs 1.2V
Introduction LCMXO3L-4300E-5UWG81CTR
MachXO3™ device family is an Ultra-Low Density family that supports the most advanced programmable bridging and I/O expansion. It has the breakthrough I/O density and the lowest cost per I/O. The device I/O features have the integrated support for latest industry standard I/O.
The LCMXO3L-4300E-5UWG81CTR MachXO3L/LF family of low power, instant-on, non-volatile PLDs has five devices with densities ranging from 640 to 9400 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. MachXO3LF devices also support User Flash Memory (UFM). These features allow these devices to be used in low cost, high volume consumer and system applications.
The LCMXO3L-4300E-5UWG81CTR MachXO3L/LF devices are designed on a 65nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family.