深圳市中立信电子科技有限公司

LC4032ZE-7TN48C

CPLD - 复杂可编程逻辑器件 32MC 32 I/O LOW PWR 1.8V 7.5ns

1.8V In-System Programmable  Ultra Low Power PLDs

Features LC4032ZE-7TN48C

 High Performance

• fMAX = 260MHz maximum operating frequency

• tPD = 4.4ns propagation delay

• Up to four global clock pins with programmable

clock polarity control

• Up to 80 PTs per output

 Ease of Design LC4032ZE-7TN48C

• Flexible CPLD macrocells with individual clock,

reset, preset and clock enable controls

• Up to four global OE controls

• Individual local OE control per I/O pin

• Excellent First-Time-FitTM and refit

• Wide input gating (36 input logic blocks) for fast

counters, state machines and address decoders

 Broad Device Offering

• 32 to 256 macrocells

• Multiple temperature range support

– Commercial: 0 to 90°C junction (Tj)

– Industrial: -40 to 105°C junction (Tj)

• Space-saving ucBGA and csBGA packages*

 Easy System Integration LC4032ZE-7TN48C

• Operation with 3.3V, 2.5V, 1.8V or 1.5V

LVCMOS I/O

• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI

interfaces

• Hot-socketing support

• Open-drain output option

• Programmable output slew rate

• 3.3V PCI compatible

• I/O pins with fast setup path

• Input hysteresis*

• 1.8V core power supply

• IEEE 1149.1 boundary scan testable

• IEEE 1532 ISC compliant

• 1.8V In-System Programmable (ISP™) using

Boundary Scan Test Access Port (TAP)

• Pb-free package options (only)

• On-chip user oscillator and timer*